This invention relates to a clock signal control circuit, a clock signal control method and a data transmission apparatus employing the control circuit and method. More Particularly, it relates to a phase error averaging circuit for pulse signals suited for clock control of an interface used in high-speed communication and to a data transmission apparatus employing the phase error averaging circuit.
Up to now, distribution of multi-phase clocks of two or more phases is by relaying and amplifying respective phase components by a circuit arrangement shown in FIG. 17a. Although not shown, complementary signals (two-phase signals) are occasionally distributed by a relay circuit adapted to cause interaction between the complementary signals. However, the clocks that can be handled by this known device are of two phases at most. Thus, should phase errors td occur as in input signals P0 to P7 as may be seen in the timing chart of FIG. 17b, an input clock is amplified with a phase error, as in the cases of Q2, or a new phase error is added to the clock, as in the case of Q5.
FIG. 18 shows an example of a digital PLL circuit for generating multi-phase or multiplied clocks. In this prior-art example, first to fourth delay circuits 901 to 904 are connected in series by first to fourth switches 905 to 908. After inputting the first clock 911, second to fifth clocks 912 to 915 are output. The fifth clock 915 is compared to the first clock 911 by a phase comparator 909. Based on an UP signal 916 or a DOWN signal 917, produced by a phase difference, a counter 910 outputs a control signal 918, which then controls the first to fourth switches 905 to 908 so that the first clock 911 and the fifth clock 915 will be close in phase to each other. This generates first to fourth clocks which are equally spaced apart four-phase clocks. In the case of multiplied clocks, the multiplied clocks are generated using these multi-phase clocks.
Although not shown in the drawings, such a system is also known in which plural delay circuits are arrayed in a ring and control is made of the number of ring steps and the number of cycling times. In this digital PLL circuit, phase errors of the multi-phase clocks produced by quantization errors of the control delay units as well as changes in the period of the multiplied clocks caused by phase errors of the multi-phase clocks are distributed straightly.
Thus, in distributing the multi-phase clocks, since there lacks the interaction between relay amplification circuits for the respective clocks, an increasing distance of distribution of the multi-phase clock signals due to the increased number of the relay amplification circuits leads to gradual increase in the error between the phases due to variations in the delay time of each relay amplification circuit, as a result of which the distributed distance of the multi-phase clocks is limited to the range of allowance of the phase errors.
FIG. 19 shows an example of application of actually distributing the multi-phase clocks. A reception circuit 1001 of FIG. 19 is such a circuit in which, for producing recovery clocks 1005 synchronized with bits of reception data 1002 as disclosed in JP Patent Kokai JP-10-190642A, a clock selection circuit 1003 selects multi-phase clocks PO to Pn, using transition points of the reception data 1001, and produces latch data 1006 using recovery clocks 1005. It is noted that the number of phases of the clocks is arbitrary and n is an integer. This reception circuit usually resides in the combination of a PLL (phase-locked loop) for generating multi-phase clocks PO to Pn and a plurality of reception circuits 1009-O to 1009-m, as shown in FIG. 20. In this case, the multi-phase clocks PO to Pn need to be routed through the reception circuits 1009-O to 1009-m. In addition, during such routing, the phase-to-phase phase difference of the multi-phase clocks needs to be kept.
FIGS. 21 and 22 show an arrangement in which reception data are captured by respective latch circuits with respective phases of the multi-phase clocks and processed in the LSI as parallel data. For outputting, the parallel data are again sequentially output as serial data.
This circuit system is disclosed in xe2x80x9cA 1.0625 Gb/s Transceiver with 2X oversampling and Transmit Signal Pre-Emphasisxe2x80x9d in ISSCC (International Solid-State Circuits Conference), 1997, pages 238 to 239. In the present system, eight-phase clocks P0 to P7 as multi-phase clocks are generated in the PLL 1102 on the receiving side, from reference clocks 1101, as shown in the block diagrams of FIG. 21 (a) and in a timing chart of FIG. 21 (b). Although the eight-phase clocks are used here, the number of phases may be changed depending on the overall circuit structure. The generated eight-phase clocks are routed to a reception circuit 1003 where input data are latched through a phase adjustment circuit 1104 by respective F/F (flip-flops). Since the frequency rate of input data is four times the frequency of each of the eight-phase clocks, the respective phases latch different values depending on changes in data. A phase comparator 1105 detects the data phase from changing points of the latched data to output a control signal 1106 which then is used in a Phase adjustment circuit 1104 so that the edges of the multi-phase clocks will be coincident with those of the data. Since one-half of data latched with the eight-phase clocks is used for detecting an optional phase change point, data detected at four phases, corresponding to every second phases, are output as parallel data.
As may be seen from the timing chart, if the input data assumes values of from D0 to D7 per period, the input data are serial/parallel converted every four bits. Also, as may be seen from the block diagram of FIG. 22 (a) and the timing chart of FIG. 22 (b), four-phase clocks of from P0 to P3, as multi-phase clocks, are generated on the transmitting side at the PLL 1202 from the reference clocks 1201. The generated four-phase clocks are routed to a transmission circuit 1203 where four parallel data are sequentially output as serial data by four parallel gates adapted to be turned on every one-fourth period.
It is seen from the timing chart that the four parallel data DQ0 to DQ7 are converted into output serial data DS0 to DS7.
In this system, since the phase components of the multi-phase clocks provide data period components, extremely stringent constraint is placed on the phase-interval errors. So, the transmission circuits and the multi-phase clock generating circuits are used frequently at a ratio of 1:1, that is one transmission circuit is used for one multi-phase clock generating circuit.
It is an object of the present invention to overcome the deficiencies of the above-mentioned prior art and to provide a novel clock signal control circuit in which it is possible to average phase errors of the respective clock signals as the phase difference between clock signals is maintained. It is another object of the present invention to provide a data transmission apparatus employing this clock signal control circuit.
For accomplishing the above objects, the present invention provides a technical configuration which is basically as defined hereinbelow.
The present invention provides a clock signal control circuit, as its first aspect, wherein multi-phase clock signals are caused to interact to average out respective phase error components of the clock signals as the phases of the respective clock signals are kept.
The present invention provides a clock signal control circuit, as its second aspect comprising a plurality of averaging circuits. Each of averaging circuits causes multi-phase clock signals to interact to average out respective phase error components of the clock signals as the phases of the respective clock signals are kept. The averaging circuits are grouped into a plurality of sets of averaging circuits, wherein each of the averaging circuit sets effects averaging in different states from one another.
The present invention provides a clock signal control circuit, as its third aspect, in which phase errors of n pulses having different phase errors are averaged out to produce n pulses having averaged phase errors, wherein two or more gates arranged in parallel are provided and outputs of the gates are interconnected to form a unit averaging circuit for averaging phase errors of two or more pulses input to the gates, n of the unit averaging circuits are provided to constitute an averaging circuit set for averaging phase errors of the n pulses, and wherein log2n stages of the averaging circuit sets are provided, there being a phase inverting circuit provided at an input of each averaging circuit of a first one of the averaging circuit sets fed with the n pulses.
The present invention provides the clock signal control circuit, as its fourth aspect, wherein the n pulses are supplied to two different unit averaging circuits of the first averaging circuit set, and wherein outputs of the unit averaging circuits of the first averaging circuit set are each fed to two different unit averaging circuits of a second averaging circuit set provided downstream of the first averaging circuit set.
The present invention provides a clock signal control circuit, as its fifth aspect, wherein outputs of respective unit averaging circuits of the averaging circuit set of a previous stage are fed to two different unit averaging circuits of the averaging circuit set provided downstream of the averaging circuit set of the previous stage.
The present invention provides a clock signal control circuit, as its sixth aspect,
wherein, in each of the unit averaging circuits of at least one averaging circuit set in the plural averaging circuit sets, signals differing in phase by xcfx80/2k radians, where k=0,1,2, . . . are averaged out.
The present invention provides a clock signal control circuit, as its seventh aspect, wherein values of the k in the respective averaging circuit sets are different from one averaging circuit set to another.
The present invention provides a clock signal control circuit, as its eighth aspect, wherein, in the respective unit averaging circuits of at least one of the averaging circuit sets, signals with phases differing by xcfx80 radians are averaged out.
The present invention provides a clock signal control circuit, as its ninth aspect, wherein each unit averaging circuit of at least one of the averaging circuit sets averages out signals having phases different by xcfx80/2 radians from one another.
The present invention provides a clock signal control circuit, as its tenth aspect,
wherein each unit averaging circuit of at least one of the averaging circuit sets averages out signals having phases neighboring (adjacent) to one another.
The present invention provides a clock signal control circuit, as its eleventh aspect, in which phase errors of n pulses having different phase errors are averaged out to produce n pulses having averaged phase errors, wherein a unit averaging circuit is formed which comprises a first differential pair, a load of each transistor of the first differential pair and a second differential pair connected in parallel with the first differential pair, each of the first and second differential pairs being fed with pulse signals having phases different from each other by xcfx80 radians to average out the phase errors of four impulses input to the first and second differential pairs, n/2 of the unit averaging circuits being provided to constitute an averaging circuit set for averaging out the phase errors of the n pulses, and wherein there are provided log2 (n/2) stages of the averaging circuit sets.
The present invention provides a clock signal control circuit, as its twelfth aspect, wherein the n pulses are fed to two different unit averaging circuits of a first one of the unit averaging circuits, and wherein outputs of respective unit averaging circuits of the first averaging circuit set are each fed to two different unit averaging circuits of a second one of the unit averaging circuits provided downstream of the first averaging circuit set.
The present invention provides a clock signal control circuit, as its thirteenth aspect, wherein outputs of respective unit averaging circuits of the upstream side averaging circuit set are each fed to different two of the unit averaging circuits provided downstream of the upstream side averaging circuit sets.
The present invention provides a clock signal control circuit, as its fourteenth aspect, in which phase errors of n pulses having different phase errors are averaged out to produce n pulses having averaged phase errors, wherein a plurality of gates connected in parallel with one another are provided, outputs of the plural gates are interconnected to constitute a first unit averaging circuit adapted for averaging out phase errors of two or more pulses input to the gates, and a plurality of such first unit averaging circuits are provided to constitute a first averaging circuit set, and wherein a second unit averaging circuit is formed which comprises a first differential pair, a load of each transistor of the first differential pair and a second differential pair connected in parallel with the first differential pair, each of the first and second differential pairs being fed with pulse signals having phases different from each other by xcfx80 radians to average out the phase errors of four pulses fed to the first and second differential pairs, there being provided n/2 second unit averaging circuits to constitute a second averaging circuit set. The respective outputs of the unit averaging circuits of the first averaging circuit set are fed to the unit averaging circuit of the second averaging circuit set.
The present invention provides a clock signal control circuit, as its fifteenth aspect, in which Phase errors of n pulses having different phase errors are averaged out to produce n pulses having averaged phase errors, wherein a first unit averaging circuit is formed which comprises a first differential pair, a load of each transistor of the first differential pair and a second differential pair connected in parallel with the first differential pair, each of the first and second differential pairs being fed with pulse signals having phases different from each other by xcfx80 radians to average out the phase errors of four impulses fed to the first and second differential pairs,
n/2 of the unit averaging circuits being provided to constitute an averaging circuit set for averaging out the phase errors of four pulses fed to the first and second differential pairs to constitute a first averaging circuit set;
a second unit averaging circuit is formed which comprises a plurality of gates arranged in parallel with one another, outputs of the plural gates being interconnected to average out phase errors of two or more pulses fed to the gates, a plurality of the second unit averaging circuits being provided to constitute a second averaging circuit set, respective outputs of the unit averaging circuits of the first averaging circuit set being adapted to be fed to the unit averaging circuits of the second averaging circuit set.
The present invention also provides a data transmission apparatus, in its first aspect, wherein multi-phase clocks generated in a multi-phase generating circuit are fed to a first device having phase error averaging circuit to average out phase errors of the multi-phase clocks as respective phases of the multi-phase clocks are kept, and wherein output of the phase error averaging circuit of the first device is fed to a second device having another phase error averaging circuit for averaging out phase errors of the multi-phase clocks under the condition that respective Phases of the multi-phase clocks fed to the second device are kept.
The present invention also provides a data transmission apparatus, in its second aspect, wherein multi-phase clocks generated in a multi-phase generating circuit are fed to a first device having phase error averaging circuit to average out phase errors of the multi-phase clocks as respective phases of the multi-phase clocks are kept, and wherein multi-phase clocks generated in the multi-phase generating circuit are fed to a second device having another phase error averaging circuit to average out phase errors of the multi-phase clocks under the condition that respective phases of the multi-phase clocks are kept.
The present invention provides a data transmission apparatus, in its third aspect, wherein the phase error averaging circuit is provided in a transmission device of a data transmission apparatus.
The present invention provides a data transmission apparatus, in its fourth aspect,
wherein the phase error averaging circuit is provided in a reception device of a data transmission apparatus.
According to a further aspect of the present invention, there is provided a method for controlling clock signals. The method comprises: providing multi-phase clock signals having phase errors, and
causing the multi-phase clock signals to interact with one another to average out phase error components of the lock signals, with the phases of the clock signals being kept.
Further aspects of the method will be apparent from the description of the foregoing aspects and the entire disclosure including the embodiments, claims and the drawings.